Synchronization refers to the requirement that transmit and receive ends of a digital communication networks operate at the same clock rate. A network clock located at transmitter node controls the rate at which data is transmitted. A second network clock located at the receiver controls the rate at which data is read. For the receiver to properly interpret incoming data, its clock needs to be synchronized to the transmitter clock.
There are different ways of synchronizing clocks over networks. In some network configurations, which are synchronous, (e.g TDM networks), transmitter clock information can be extracted directly from the data and used in the receiver to synchronize the two clocks. Due to low cost and availability of packet networks, many service providers are looking into transporting legacy services (such as TDM services) over IP based networks. The main problem is how to maintain the same level of synchronization as in legacy network. Although there are different approaches for solving this problem but the one approach that has potential many advantages over the others (including cost and availability) is clock synchronization over packet networks using dedicated timing packets.
FIG. 1 shows an illustration of this approach. At the transmitter side dedicated timing packets are time-stamped by the transmitter's clock and then are sent over the packet switched network (PSN) to one or multiple receivers. At the receiver side these timing packets are time-stamped by the receiver clock as they arrive. The difference between these two times tamps represents the relative delay between transmitter and receiver's clocks, which then can be used to synchronizes the two clocks. Among advantages of this approach are the fact that it does not require extra means or modification of the physical layer for synchronizing the clocks and that fact that it is widely available (as long as there is IP network). Nonetheless this approach has its own challenges.
One of the main challenges in this synchronization approach is that the timing packets are subjected to packet delay variations (PDV) inherent to any packet switched network. As a result, at the receiver side, depending on packet delay variations, the recovered reference clock will have high level of jitter and wander, which is not acceptable for many applications, especially legacy services that require high quality level of synchronization.
To overcome this issue, prior art suggest methods based on filtering timing packets at the receiver such that only those timing packets that are least subjected to packet delay variations used for clock recovery.
U.S. Pat. No. 6,658,025 describes a method for filtering timing packets where the expected arrival time for each timing packet is estimated and compared to the actual arrival time. A number of timing packets with most deviations from expected value are then discarded and the remaining timing packets are used to recalculate a new expected value for arrival time. The new calculated expected value again is used to discard a new series of timing packets and this process continues until a certain number of timing packets have been discarded. In this elimination process, the remaining timing packets are used to correct any frequency offset between transmitter and receiver clocks.
U.S. Pat. No. 7,315,546 discloses a method that, instead of discarding timing packets, uses a weighted set of timing packets to synchronize the receiver and transmitter clocks. Weightings are calculated based on the distance between the expected arrival time and the actual arrival time of the timing packets in this fashion that timing packets with largest distance from expected delay will be given least amount of weighting.
Clock recovery performance of above methods and other prior art is susceptible to network PDV and at times it cannot be guaranteed for certain network PDVs that usually exists because of high traffic loading (e.g when network is loaded with 80% or more of traffic). A common solution to this is to stop the clock recovery algorithm during these high traffic periods and put the algorithm into hold-over mode where it will update the DCO using a fixed value based on the past DCO update values. A drawback of this approach is that it will result in phase and frequency drift of output clock.